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Espressif Systems /ESP32-S3 /SYSTEM /PERIP_CLK_EN0

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Interpret as PERIP_CLK_EN0

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31282724232019161512118743000000000000000000000000000000000000000000 (TIMERS_CLK_EN)TIMERS_CLK_EN0 (SPI01_CLK_EN)SPI01_CLK_EN0 (UART_CLK_EN)UART_CLK_EN0 (WDG_CLK_EN)WDG_CLK_EN0 (I2S0_CLK_EN)I2S0_CLK_EN0 (UART1_CLK_EN)UART1_CLK_EN0 (SPI2_CLK_EN)SPI2_CLK_EN0 (I2C_EXT0_CLK_EN)I2C_EXT0_CLK_EN0 (UHCI0_CLK_EN)UHCI0_CLK_EN0 (RMT_CLK_EN)RMT_CLK_EN0 (PCNT_CLK_EN)PCNT_CLK_EN0 (LEDC_CLK_EN)LEDC_CLK_EN0 (UHCI1_CLK_EN)UHCI1_CLK_EN0 (TIMERGROUP_CLK_EN)TIMERGROUP_CLK_EN0 (EFUSE_CLK_EN)EFUSE_CLK_EN0 (TIMERGROUP1_CLK_EN)TIMERGROUP1_CLK_EN0 (SPI3_CLK_EN)SPI3_CLK_EN0 (PWM0_CLK_EN)PWM0_CLK_EN0 (I2C_EXT1_CLK_EN)I2C_EXT1_CLK_EN0 (TWAI_CLK_EN)TWAI_CLK_EN0 (PWM1_CLK_EN)PWM1_CLK_EN0 (I2S1_CLK_EN)I2S1_CLK_EN0 (SPI2_DMA_CLK_EN)SPI2_DMA_CLK_EN0 (USB_CLK_EN)USB_CLK_EN0 (UART_MEM_CLK_EN)UART_MEM_CLK_EN0 (PWM2_CLK_EN)PWM2_CLK_EN0 (PWM3_CLK_EN)PWM3_CLK_EN0 (SPI3_DMA_CLK_EN)SPI3_DMA_CLK_EN0 (APB_SARADC_CLK_EN)APB_SARADC_CLK_EN0 (SYSTIMER_CLK_EN)SYSTIMER_CLK_EN0 (ADC2_ARB_CLK_EN)ADC2_ARB_CLK_EN0 (SPI4_CLK_EN)SPI4_CLK_EN

Description

peripheral clock configuration regsiter 0

Fields

TIMERS_CLK_EN

Set 1 to enable TIMERS clock
SPI01_CLK_EN

Set 1 to enable SPI01 clock
UART_CLK_EN

Set 1 to enable UART clock
WDG_CLK_EN

Set 1 to enable WDG clock
I2S0_CLK_EN

Set 1 to enable I2S0 clock
UART1_CLK_EN

Set 1 to enable UART1 clock
SPI2_CLK_EN

Set 1 to enable SPI2 clock
I2C_EXT0_CLK_EN

Set 1 to enable I2C_EXT0 clock
UHCI0_CLK_EN

Set 1 to enable UHCI0 clock
RMT_CLK_EN

Set 1 to enable RMT clock
PCNT_CLK_EN

Set 1 to enable PCNT clock
LEDC_CLK_EN

Set 1 to enable LEDC clock
UHCI1_CLK_EN

Set 1 to enable UHCI1 clock
TIMERGROUP_CLK_EN

Set 1 to enable TIMERGROUP clock
EFUSE_CLK_EN

Set 1 to enable EFUSE clock
TIMERGROUP1_CLK_EN

Set 1 to enable TIMERGROUP1 clock
SPI3_CLK_EN

Set 1 to enable SPI3 clock
PWM0_CLK_EN

Set 1 to enable PWM0 clock
I2C_EXT1_CLK_EN

Set 1 to enable I2C_EXT1 clock
TWAI_CLK_EN

Set 1 to enable CAN clock
PWM1_CLK_EN

Set 1 to enable PWM1 clock
I2S1_CLK_EN

Set 1 to enable I2S1 clock
SPI2_DMA_CLK_EN

Set 1 to enable SPI2_DMA clock
USB_CLK_EN

Set 1 to enable USB clock
UART_MEM_CLK_EN

Set 1 to enable UART_MEM clock
PWM2_CLK_EN

Set 1 to enable PWM2 clock
PWM3_CLK_EN

Set 1 to enable PWM3 clock
SPI3_DMA_CLK_EN

Set 1 to enable SPI4 clock
APB_SARADC_CLK_EN

Set 1 to enable APB_SARADC clock
SYSTIMER_CLK_EN

Set 1 to enable SYSTEMTIMER clock
ADC2_ARB_CLK_EN

Set 1 to enable ADC2_ARB clock
SPI4_CLK_EN

Set 1 to enable SPI4 clock

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data